1. Field of the Invention
The present invention relates to a semiconductor package, more specifically to a semiconductor package having a sufficient strength to thermal shock.
2. Description of Related Art
Conventionally, it has been required to mount a semiconductor chip such as an integrated circuit chip (hereinafter referred to as an IC chip) or a light emitting diode chip (hereinafter referred to as an LED chip) on a base material such as a PCB substrate or an MID (Molded Interconnect Device) substrate, or the like, by flip chip (hereinafter referred to as FC) bonding in order to miniaturize a semiconductor package. However, because thermal expansion coefficients of a material of the semiconductor chip such as the IC chip and a material of the PCB substrate or thermal expansion coefficients of the material of the IC chip and a material of the MID substrate are vastly different, there is a problem in that a connecting part of the IC chip and a wiring on each substrate is easily broken due to the thermal stress generated between the IC chip and the PCB substrate or the MID substrate during operations.
More specifically, if the IC 12 chip having bumps 10 formed on its terminals (not shown) is mounted on the PCB substrate 14 by FC bonding, as shown in FIG. 2A, connecting portions of the IC chip and the PCB substrate through the bumps 10 are easily broken due to thermal shock, because a thermal expansion coefficient of silicon which is a main material of the IC chip 12 is about 3 ppm/° C., and a thermal expansion coefficient of glass epoxy or BT resin which is a main material of the PCB substrate is about 12 to 17 ppm/° C.
Moreover, if a copper wiring or a copper pattern 18 is formed by plating on the MID substrate 16 formed as a molded resin article and the IC chip 12 in which the bumps 10 are formed on terminals thereof is mounted on the MID substrate 16 by FC bonding, as shown in FIG. 2B, then, since a thermal expansion coefficient of a resin which is a main material of the MID substrate is about 40 ppm/° C., the strength of the package shown in FIG. 2B against thermal shock is decreased is even more than that of the package shown in FIG. 2A.
To resolve the above-described of resistance to thermal shock in the semiconductor package, a method for mounting the IC chip 12 provided with the bumps 10 on a ceramic substrate 8 provided with the copper pattern by FC bonding has also been used as shown in FIG. 2C. A thermal expansion coefficient of the ceramic substrate 8 is about 7 ppm/° C., which is approximately the same as that of silicon, therefore a high strength is acquired. However, there is a problem in that the manufacturing costs of the semiconductor package become very high and the products to which the method is applicable are limited.
To resolve this problem, a proposal there has been disclosed in which a thermal stress generated by a difference between thermal expansion coefficients of an IC chip and a base material is reduced by using a soldering bump having a high temperature fusion point and using a material having a small Young's modulus for a solder of the soldering bump (for reference, see Japanese Patent Laid-Open H8-64717).
However, there is a limitation on the degree to which the Young's modulus of the soldering bump, can be lowered hence it is difficult to obtain a sufficient strength in the IC chip and so on even if the means described above is used.
A proposal has also been disclosed in which generation of stress is reduced when manufacturing a semiconductor package by maintaining an IC chip and a substrate at a high temperature when manufacturing the semiconductor (for reference, see Japanese Patent Laid-Open H11-126796). However, even if the semiconductor package is manufactured by such a method, a semiconductor package having a small stress can be made at the beginning of manufacturing thereof, but stress is still generated by a difference between thermal expansion coefficients of the IC chip and the base material in thermal history after the semiconductor package has been manufactured.
Moreover, a proposal has been disclosed in which an IC chip is mounted on a flexible printed circuit (hereinafter referred to as FPC) substrate by FC bonding and electrodes of the FPC substrate and electrodes of a PCB substrate are connected through a sheet of an anisotropic conductive elastic body, as a result, any stress generated by a difference between thermal expansion coefficients of the IC chip and the PCB substrate is reduced by elastic function of the sheet of the anisotropic conductive elastic body (for reference, see Japanese Patent Laid-Open 2001-203237).
This method produces a greater for thermal stress reduction effect. However, connecting the electrodes of the FPC substrate and the PCB substrate through a sheet of an anisotropic conductive elastic body is a technology for producing an advantageous effect when used for a semiconductor package having a great number of pins; if it is used for a semiconductor package having a small number of pins, there is a problem in that a semiconductor package with a small number of pins is more expensive than a case where a ceramic substrate is used.
Furthermore, it has been required that a concave portion or hole for arranging a light-emitting member is provided in a base material of a semiconductor package and a reflecting film is provided in the concave portion and so on, in order to increase luminous efficiency in the light-emitting member such as an LED chip (for reference, see Japanese Patent Laid-Open 2003-163378). However, because the base material having such a concave portion is, for reasons of cost, made of a resin with high thermal expansion coefficient, a problem arises, regarding a thermal stress generated by a difference in the thermal expansion coefficients of the light-emitting member and the base material, which just as serious as that described above.